Jove
Visualize
Contact Us

Related Concept Videos

Neural Regulation01:37

Neural Regulation

40.4K
Digestion begins with a cephalic phase that prepares the digestive system to receive food. When our brain processes visual or olfactory information about food, it triggers impulses in the cranial nerves innervating the salivary glands and stomach to prepare for food.
40.4K
Neural Circuits01:25

Neural Circuits

1.7K
Neural circuits and neuronal pools are two of the main structures found in the nervous system. Neural circuits are networks of neurons that work together to carry out a specific task or process. They consist of interconnected neurons and glial cells, which provide structural and metabolic support.
Neuronal pools are collections of nerve cells with similar functions and interact through chemical and electrical signals. These pools include both interneurons (the central neural circuit nodes that...
1.7K

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

The Role of Hydrogen in ReRAM.

Advanced materials (Deerfield Beach, Fla.)·2024
Same author

Hardware implementation of memristor-based artificial neural networks.

Nature communications·2024
Same author

Thin-film design of amorphous hafnium oxide nanocomposites enabling strong interfacial resistive switching uniformity.

Science advances·2023
Same author

Brain-inspired computing needs a master plan.

Nature·2022
Same author

Committee machines-a universal method to deal with non-idealities in memristor-based neural networks.

Nature communications·2020
Same author

Silicon Oxide (SiO<sub>x</sub> ): A Promising Material for Resistance Switching?

Advanced materials (Deerfield Beach, Fla.)·2018
Same journal

Overcoming the Catalytic Bucket Effect in Pt-based High-Entropy Nanocages Through Interface Defect and Strain Engineering.

Advanced science (Weinheim, Baden-Wurttemberg, Germany)·2026
Same journal

Rare-Earth-Sulfur Surface Modification Enables SiC Ceramics for Low-Frequency Electromagnetic Wave Absorption in Extreme Environments.

Advanced science (Weinheim, Baden-Wurttemberg, Germany)·2026
Same journal

PFKFB4 Deubiquitination by USP10 Enhances Fumarate Metabolism to Orchestrate the KDM1A/Rad51 Axis and Confer Radioresistance in Lung Cancer.

Advanced science (Weinheim, Baden-Wurttemberg, Germany)·2026
Same journal

Assessing Strengths and Limitations of Magnetoencephalography Source Imaging With Intracerebral EEG.

Advanced science (Weinheim, Baden-Wurttemberg, Germany)·2026
Same journal

Efficient Adsorption-Based Direct Air Capture Via Triply Periodic Minimal Surface Architectures.

Advanced science (Weinheim, Baden-Wurttemberg, Germany)·2026
Same journal

Inhalable ROS-Responsive Nanospray Activates PPAR-γ to Restore Macrophage Mitochondrial Homeostasis and Attenuate Radiation-Induced Lung Injury.

Advanced science (Weinheim, Baden-Wurttemberg, Germany)·2026
See all related articles
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Experiment Video

Updated: Sep 24, 2025

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

8.0K

Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks.

Dovydas Joksas1, Erwei Wang2,3, Nikolaos Barmpatsalos1

  • 1Department of Electronic and Electrical Engineering, University College London, London, WC1E 7JE, UK.

Advanced Science (Weinheim, Baden-Wurttemberg, Germany)
|May 4, 2022
PubMed
Summary
This summary is machine-generated.

This study introduces a training method for artificial intelligence hardware that accounts for physical imperfections in memristor components. By adjusting how these systems learn, researchers achieved significantly higher energy efficiency without sacrificing accuracy.

Keywords:
hardware accelerationmemristorsneural networksanalog computingenergy efficiencymachine learning hardwarecrossbar arrays

Frequently Asked Questions

More Related Videos

A Method for Growing Bio-memristors from Slime Mold
07:46

A Method for Growing Bio-memristors from Slime Mold

Published on: November 2, 2017

9.1K
Closed-loop Neuro-robotic Experiments to Test Computational Properties of Neuronal Networks
11:18

Closed-loop Neuro-robotic Experiments to Test Computational Properties of Neuronal Networks

Published on: March 2, 2015

10.5K

Related Experiment Videos

Last Updated: Sep 24, 2025

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

8.0K
A Method for Growing Bio-memristors from Slime Mold
07:46

A Method for Growing Bio-memristors from Slime Mold

Published on: November 2, 2017

9.1K
Closed-loop Neuro-robotic Experiments to Test Computational Properties of Neuronal Networks
11:18

Closed-loop Neuro-robotic Experiments to Test Computational Properties of Neuronal Networks

Published on: March 2, 2015

10.5K

Area of Science:

  • Neuromorphic engineering within memristive neural networks research
  • Computer architecture and hardware acceleration systems

Background:

Artificial intelligence systems currently demand massive computational resources to perform complex cognitive tasks effectively. This high energy consumption drives the search for alternative hardware architectures beyond traditional digital processors. Memristor-based crossbar arrays offer a promising path toward highly efficient analog data processing. Yet, these physical devices suffer from inherent nonidealities that frequently compromise computational precision. Prior research has shown that standard training techniques fail to compensate for these hardware-specific variations. That uncertainty drove the development of specialized mitigation strategies to preserve system performance. No prior work had resolved the conflict between achieving extreme power savings and maintaining robust reliability. This gap motivated the creation of a training framework that explicitly incorporates device limitations during the learning process.

Purpose Of The Study:

The study aims to develop a training framework that accounts for physical device imperfections in memristor-based neural networks. Researchers sought to address the degradation of accuracy caused by inherent hardware nonidealities. This project was motivated by the need to balance energy efficiency with computational reliability in cognitive hardware. The authors investigated whether high-resistance devices with significant nonlinearity could be utilized effectively in these systems. They aimed to demonstrate that incorporating device limitations into the learning process preserves overall network performance. The team addressed the trade-offs between power consumption and operational stability that often limit current analog accelerators. This work provides a systematic solution for managing common device variations during the training phase. The researchers intended to show that their approach is both universal and robust for various types of hardware nonidealities.

Main Methods:

The review approach focuses on developing a training methodology that accounts for physical device limitations. Researchers integrated common hardware nonidealities directly into the network optimization process to improve system robustness. They utilized experimental measurements of memristor characteristics to inform the mathematical models used during training. The team implemented regularization techniques to bias individual devices toward more energy-efficient, less conductive states. Validation procedures were adjusted to provide more precise estimates of performance under realistic operating conditions. This design strategy allows the network to adapt to the specific behaviors of the underlying physical substrate. The study evaluates the feasibility of using high-resistance components that display significant current-voltage nonlinearity. This systematic approach ensures that the resulting neural architectures remain accurate despite the inherent imperfections of analog hardware.

Main Results:

Key findings from the literature indicate that the proposed training method improves energy efficiency by nearly three orders of magnitude. The system achieved an efficiency of 381 TOPs per watt compared to the baseline of 0.715 TOPs per watt. This substantial gain in power performance occurred while maintaining accuracy levels similar to those of ideal systems. The authors show that associating network parameters with specific memristors enables effective bias control. Regularizing the optimization problem successfully shifts devices toward less conductive states without degrading computational output. The researchers confirmed that their validation modifications lead to more reliable performance estimates for these hardware structures. The study demonstrates that high-resistance devices with high nonlinearity are practical for large-scale neural network deployment. These results confirm the robustness of the training framework when applied to a diverse range of device imperfections.

Conclusions:

The authors propose that their training framework effectively manages common device imperfections in analog hardware. This synthesis suggests that high-resistance components with significant nonlinearity are viable for future neural architectures. The researchers demonstrate that linking network parameters to specific memristors enables biasing toward more efficient states. Regularizing the optimization problem provides a pathway to minimize power consumption while preserving computational integrity. Modifying validation procedures ensures that performance metrics reflect real-world operational conditions more accurately. This approach highlights the potential for massive gains in energy efficiency for vector-matrix multiplication tasks. The findings imply that hardware-aware learning is a robust solution for deploying neural networks on non-ideal physical substrates. Future implementations could leverage these insights to scale cognitive computing systems with reduced energy footprints.

The researchers propose a training framework that incorporates device-specific imperfections into the learning process. This method biases memristors toward less conductive states through regularization, which significantly improves energy efficiency while maintaining accuracy levels comparable to ideal systems.

The study utilizes memristive vector-matrix multipliers as the primary hardware component. These structures leverage analog data processing to achieve performance improvements, contrasting with traditional digital architectures that typically require higher power for equivalent computational throughput.

High-resistance devices exhibiting significant current-voltage nonlinearity are necessary to achieve the reported energy efficiency gains. The authors demonstrate that these specific characteristics can be successfully managed through their proposed training methodology.

The authors employ experimental data to validate their training framework. This data serves as the foundation for estimating the energy efficiency improvements, allowing for a direct comparison between standard training and their nonideality-aware methodology.

The researchers measured energy efficiency in terms of tera-operations per second per watt. They observed an improvement from 0.715 TOPs per watt to 381 TOPs per watt, representing a nearly three-order-of-magnitude increase in efficiency.

The authors claim that their approach is universal and robust across a wide range of device nonidealities. They suggest this methodology provides a reliable path for deploying neural networks on hardware that would otherwise be considered too unreliable for practical use.