High-κ perovskite membranes as insulators for two-dimensional transistors.

Area of Science:

• Materials Science
• Semiconductor Physics
• Nanotechnology

Background:

• Silicon scaling in transistors faces challenges like leakage currents at sub-ten-nanometre nodes.
• Two-dimensional (2D) semiconductors offer potential for future transistors due to their atomic thickness.
• Integrating high-dielectric-constant (κ) materials with 2D semiconductors while maintaining low capacitance equivalent thickness (CET) is difficult.

Purpose of the Study:

• To explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as gate dielectrics for 2D field-effect transistors.
• To address the challenges in integrating high-κ dielectrics with 2D materials for advanced transistor applications.

Main Methods:

• Fabrication of ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes.
• Integration of these membranes as gate dielectrics with 2D semiconductor channel materials.
• Characterization of transistor performance, including capacitance equivalent thickness (CET), leakage current, subthreshold swing, and on/off current ratios.

Main Results:

• Perovskite membranes achieved sub-one-nanometre CET with low leakage current (<10⁻² A/cm² at 2.5 MV/cm).
• The van der Waals gap between the dielectric and 2D semiconductor mitigated fringing-induced barrier lowering.
• Transistors demonstrated steep subthreshold swings (~70 mV/decade) and high on/off ratios (up to 10⁷).

Conclusions:

• Ultrahigh-κ strontium-titanium-oxide membranes are promising gate dielectrics for 2D field-effect transistors.
• The developed materials meet the low-power specifications outlined in the International Roadmap for Devices and Systems.
• This work advances the development of next-generation transistors beyond traditional silicon scaling.