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A Circuit Model for Working Memory Based on Hybrid Positive and Negative-Derivative Feedback Mechanism
Hui Wei1,2, Xiao Jin1,2, Zihao Su1,2
1Laboratory of Cognitive Model and Algorithm, Department of Computer Science, Fudan University, No. 825 Zhangheng Road, Shanghai 201203, China.
This study introduces a novel neural network model for working memory (WM). The hybrid positive and negative-derivative feedback (HPNF) model enhances robustness for information storage and updating in neural circuits.
Area of Science:
- Cognitive Neuroscience
- Computational Neuroscience
- Neural Networks
Background:
- Working memory (WM) is crucial for learning and decision-making, supporting daily tasks like remembering codes.
- Existing WM models often rely on synapse parameters, limiting robustness.
- Understanding WM at the microscopic neural level requires advanced computational models.
Purpose of the Study:
- To design a microscopic neural network model explaining the internal mechanisms of working memory.
- To develop a more robust WM model using a hybrid feedback mechanism.
- To simulate information storage, association, updating, and forgetting at the neural circuit level.
Main Methods:
- Developed a hybrid positive and negative-derivative feedback (HPNF) model to enhance robustness against disturbances.
- Constructed a memory-storage sub-network (SET) utilizing positive feedback and negative-derivative feedback.
- Designed a storage distribution network (SDN) integrating SET for memory operations.
Main Results:
- The SET network demonstrates robustness in self-sustaining neural information.
- The SDN effectively constructs a storage distribution network at the neural circuit level.
- The model successfully simulates information storage, association, updating, and forgetting.
Conclusions:
- The proposed HPNF-based neural network model provides a robust mechanism for working memory functions.
- The model demonstrates adaptability across different individuals with minimal parameter adjustments.
- This work advances our understanding of working memory at the neural circuit level.
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