Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Area of Science:

• Electrical Engineering
• Computer Engineering
• Materials Science

Background:

• Embedded dynamic random-access memory (eDRAM) is crucial for processing-in-memory (PIM) applications.
• Conventional eDRAM cells face limitations in data retention time and area efficiency due to bulky capacitors.
• Deep-submicron processes exacerbate leakage currents, impacting memory cell stability and performance.

Purpose of the Study:

• To develop a novel pseudo-static gain cell (PS-GC) for eDRAM macros.
• To achieve extended/unlimited data retention time, overcoming conventional eDRAM limitations.
• To enhance area efficiency and access speeds for analog PIM applications.

Main Methods:

• Design of a two-transistor (2T) gain cell with active leakage compensation.
• Implementation of a 64x64 eDRAM macro using the proposed PS-GC in a 28nm CMOS process.
• Post-layout simulations to evaluate retention time, access speed, power consumption, and operational stability across process, voltage, and temperature variations.

Main Results:

• The PS-GC demonstrates unlimited retention time, comparable to Static RAM (SRAM).
• Achieved bitcell area is 0.79x that of 6T SRAM and 0.58x that of 8T STAM.
• Simulations confirm stable pseudo-static operation across wide process, voltage, and temperature ranges (-25 to 85 °C).
• Write-access and read-access times below 0.3 ns at 667 MHz and 85 °C.
• Static power consumption of 2.2 nW/bit at 25 °C.

Conclusions:

• The PS-GC effectively compensates for leakage currents, enabling unlimited retention in eDRAM.
• The proposed eDRAM cell significantly improves area efficiency for analog PIM.
• The design offers accelerated access times and robust performance, suitable for advanced integrated circuits.