An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent...

Area of Science:

• Integrated Circuits
• Computer Architecture
• Semiconductor Devices

Background:

• Dynamic random-access memory (eDRAM) is crucial for high-speed computing.
• Processing-in-memory (PIM) architectures aim to reduce data movement bottlenecks.
• Existing eDRAM designs face limitations in retention time and access speed.

Purpose of the Study:

• To introduce a novel n-type pseudo-static gain cell (PS-nGC) for enhanced eDRAM.
• To improve retention time and reduce access times in eDRAM for PIM.
• To evaluate the performance and versatility of the proposed PS-nGC.

Main Methods:

• Implementation of a two-transistor (2T) gain cell with n-type pseudo-static leakage compensation (n-type PSLC).
• Utilized a homogeneous NMOS-based 2T gain cell and a boosted write wordline technique.
• Fabricated the design using a 28 nm complementary metal oxide semiconductor (CMOS) process.

Main Results:

• Achieved 3.27x reduction in write access time and 1.81x reduction in read access time compared to previous designs.
• Demonstrated stable operation across a wide supply voltage range (0.7-1.2 V) at 667 MHz.
• Achieved a compact bitcell area of 0.284 µm² for a 4 kb eDRAM macro.

Conclusions:

• The proposed PS-nGC offers significant improvements in speed and retention for eDRAM.
• The design is versatile, supporting a broad voltage range and maintaining performance under varying conditions.
• PS-nGC is a promising solution for high-speed PIM applications requiring efficient eDRAM.