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    This study optimizes machine learning classifiers for resource-constrained embedded Internet of Things (IoT) devices. Reducing numerical precision significantly cuts computational costs without sacrificing model performance, enabling efficient edge computing applications.

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    Area of Science:

    • Computer Science
    • Electrical Engineering
    • Embedded Systems

    Background:

    • The proliferation of Internet of Things (IoT) devices generates vast data, driving the need for on-device machine learning.
    • Computational complexity of geometric classifiers hinders their deployment on resource-limited embedded systems.
    • Existing methods face challenges in balancing performance and resource constraints for industrial edge applications.

    Purpose of the Study:

    • To evaluate strategies for reducing the implementation costs of classifiers on embedded edge devices.
    • To analyze the trade-off between numerical precision and model performance for distance-based classifiers.
    • To develop and assess a novel hardware architecture for efficient classifier implementation.

    Main Methods:

    • Evaluation of classifier implementation costs using the CHIP-clas model, independent of hyperparameter tuning.
    • Comparison of 16-bit floating-point formats against 32-bit precision for a distance-based classifier.
    • Development and benchmarking of a new hardware architecture against state-of-the-art references.

    Main Results:

    • The CHIP-clas model demonstrates robustness to reduced numerical precision (16-bit floating-point).
    • Statistically equivalent model performance was achieved with lower precision compared to the baseline 32-bit implementation.
    • The new hardware architecture resulted in a significant speed-up factor of approximately 4.39 in processing time.

    Conclusions:

    • Reduced numerical precision is a viable strategy for optimizing machine learning classifiers on embedded edge devices.
    • The proposed approach enables efficient deployment of complex classifiers in resource-constrained IoT applications.
    • The developed hardware architecture offers substantial performance improvements for embedded edge computing.