FPGA-Based Pedestrian Detection for Collision Prediction System.

Area of Science:

• Computer Vision
• Embedded Systems
• Automotive Safety

Background:

• Existing pedestrian detection (PD) systems require improvements in speed and range for effective pedestrian collision prediction (PCP).
• Enhanced decision-making distance in PCP systems is critical for preventing collisions.

Purpose of the Study:

• To propose a performance-optimized FPGA implementation of a HOG-SVM-based PD system.
• To enhance PCP systems by improving PD capabilities for near and far pedestrians.
• To increase the decision-making distance in PCP systems.

Main Methods:

• Developed a hardware architecture for PD processing one pixel per clock cycle using data and temporal parallelism (pipelining, spatial division).
• Implemented a HOG-SVM-based PD system on FPGA with support for image pyramids and multi-sized detection windows.
• Integrated the PD module with a stereo semi-global matching (SGM) module prototyped on FPGA.

Main Results:

• The proposed PD system achieved 100 FPS in HD resolution.
• The integrated PCP system achieved 66.2 FPS, a significant improvement over 30 FPS systems.
• Using two detection window sizes reduced the miss rate by at least 6% compared to single-sized windows.

Conclusions:

• The FPGA-based PD system significantly enhances PCP system performance.
• The optimized architecture enables faster and more accurate detection of pedestrians at various distances.
• The system increases the decision-making distance by 3.3 m, improving overall road safety.