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Published on: October 23, 2018
Synaptic Segmented Transistor with Improved Linearity by Schottky Junctions and Accelerated Speed by Double-Layered
Seong-Yeon Kim1,2, Ji-Man Yu1, Gi Sung Lee3
1School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
Researchers developed a novel segmented transistor for artificial synapses, improving linearity and speed. This silicon-based device advances the mass production of neuromorphic computing hardware.
Area of Science:
- Materials Science
- Electrical Engineering
- Computer Science
Background:
- Neuromorphic computing aims to overcome von Neumann architecture limitations for artificial intelligence.
- Synaptic devices are crucial for hardware integration in neuromorphic systems, requiring high compactness and silicon-based memory for mass production.
- Existing silicon-based synaptic devices face challenges in linearity and operational speed.
Purpose of the Study:
- To propose a novel segmented transistor for artificial synapses to enhance the linearity of potentiation and depression (P/D).
- To improve the operational speed of synaptic devices through innovative material engineering.
- To advance the development of CMOS-compatible synaptic devices for potential mass production.
Main Methods:
- A complementary metal oxide semiconductor (CMOS)-compatible segmented transistor architecture was designed and fabricated.
- Non-ohmic Schottky junctions at the source and drain were utilized to improve weight linearity.
- A double-layered nitride (SiN) charge trap layer with varied stoichiometries was employed to boost operation speed.
- Drain current-gate voltage transfer characteristics were analyzed to identify distinct operational segments.
Main Results:
- The proposed segmented transistor exhibits three distinct segments in its drain current-gate voltage transfer characteristics, attributed to the Schottky junctions.
- The use of double-layered nitride with different stoichiometries significantly enhanced the operation speed of the artificial synapse.
- The device demonstrated improved linearity in potentiation and depression, crucial for accurate synaptic weight updates.
- The CMOS-compatible nature of the device facilitates integration with existing semiconductor fabrication processes.
Conclusions:
- The novel segmented transistor design successfully addresses key limitations in artificial synaptic devices, particularly linearity and speed.
- This silicon-based device represents a significant step towards the realization of mass-produced, hardware-based neuromorphic systems.
- The integration of Schottky junctions and tailored nitride layers offers a promising pathway for future neuromorphic hardware development.
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