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A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator.
Deeksha Verma1, Khuram Shehzad1,2, Sung Jin Kim1,2
1Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.
This study presents a 10-bit asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) achieving 9.49 bits effective resolution. The design optimizes power and performance using novel techniques for high-speed, low-power applications.
Area of Science:
- Electrical Engineering
- Integrated Circuit Design
- Signal Processing
Background:
- Analog-to-Digital Converters (ADCs) are crucial components in mixed-signal systems.
- Optimizing power consumption and performance (speed, linearity) in ADCs remains a significant challenge.
- Successive Approximation Register (SAR) ADCs offer a balance of resolution and speed, but further improvements are sought.
Purpose of the Study:
- To propose and validate a novel 10-bit asynchronous SAR ADC prototype with an integrated bandgap reference voltage generator.
- To enhance power efficiency, static, and dynamic performance through innovative design techniques.
- To achieve high-speed conversion without relying on external high-frequency clocks.
Main Methods:
- Fabrication of a 10-bit 1 MS/s SAR ADC prototype using 130 nm technology.
- Implementation of a dual-path bootstrap switch for improved sampling linearity.
- Utilization of a Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique to reduce switching energy.
- Adoption of a two-stage dynamic latch comparator architecture for high speed and low power.
- Integration of asynchronous SAR logic with an internally generated clock for efficient time sequencing and single-cycle conversion.
- Inclusion of an error amplifier-based bandgap reference voltage generator for stable reference voltage.
Main Results:
- The fabricated SAR ADC achieved an Effective Number of Bits (ENOB) of 9.49 bits.
- A Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB was measured.
- The ADC operated at a sampling rate of 1 MS/s with a 1.2 V power supply.
- The proposed design successfully integrated an on-chip bandgap reference voltage generator.
Conclusions:
- The developed asynchronous SAR ADC demonstrates competitive performance in terms of resolution and speed.
- The implemented techniques effectively address power consumption and linearity challenges in SAR ADCs.
- The integrated bandgap reference enhances the practicality and reduces the system complexity of the ADC.
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