Bisection Neural Network Toward Reconfigurable Hardware Implementation.

Area of Science:

• Computer Science
• Electrical Engineering
• Artificial Intelligence

Background:

• Conventional reconfigurable fully connected neural network (FC-NN) circuit topologies face hardware limitations due to numerous synapse connections.
• Implementing complex functions on-chip requires efficient neural network (NN) architectures.

Purpose of the Study:

• To propose a hardware-friendly bisection neural network (BNN) topology for efficient implementation of complex functions.
• To demonstrate the equivalence between FC-NN and BNN circuit topologies for NN behaviors.
• To reduce the number of neurons and synapses for ultra-efficient hardware implementations.

Main Methods:

• Developed a bisection structure where each neuron has two constant synapse connections.
• Proved the migration of NN behaviors from FC-NN to BNN topologies.
• Introduced a refining training algorithm and an inverted-pyramidal strategy for optimization.
• Conducted inaccuracy tolerance analysis for hardware implementation guidelines.

Main Results:

• The proposed BNN topology eliminates significant dummy synapse connections compared to FC-NN.
• Achieved 17.8–22.2× hardware reduction versus the TrueNorth FC-NN baseline.
• Maintained less than 1% inaccuracy in implemented functions.

Conclusions:

• The hardware-friendly BNN topology provides a viable and efficient alternative for implementing complex functions on-chip.
• BNN offers substantial hardware savings and minimal accuracy loss, paving the way for ultra-efficient hardware implementations.