A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Digital Signal Processing

Background:

• Traditional analog-to-digital converters (ADCs) often require external components, increasing complexity and cost.
• Field-programmable gate arrays (FPGAs) offer reconfigurability but integrating high-performance ADCs can be challenging.
• Variations in process, voltage, and temperature (PVT) significantly impact ADC performance and stability.

Purpose of the Study:

• To propose a novel slope analog-to-digital converter (ADC) that can be fully implemented on a digital field-programmable gate array (FPGA).
• To develop an online calibration algorithm to enhance the ADC's robustness against PVT variations.
• To characterize the performance of the proposed FPGA-based ADC prototype.

Main Methods:

• A slope ADC architecture is designed for complete FPGA implementation, utilizing an LVDS differential input.
• Amplitude information is encoded in transition times, retrieved by an on-chip time-to-digital converter (TDC).
• A new online calibration algorithm is developed and integrated to compensate for environmental and manufacturing variations.

Main Results:

• The prototype ADC demonstrates an analog input range of 0.3 V to 1.5 V with a least significant bit (LSB) of 2.6 mV.
• An effective number of bits (ENOB) of 7.4-bit was achieved at a sampling rate of 600 MS/s.
• Excellent linearity was observed, with differential nonlinearity (DNL) between -0.78 and 0.70 LSB, and integral nonlinearity (INL) from -0.72 to 0.78 LSB.

Conclusions:

• The proposed fully FPGA-based slope ADC offers a component-free solution for high-speed analog-to-digital conversion.
• The integrated online calibration algorithm effectively mitigates performance degradation due to PVT variations.
• The ADC prototype exhibits competitive performance metrics, suitable for various digital signal processing applications.