PIC micro-controller based synchronization of two fractional order jerk systems
Samuel Tagne1, Bertrand Bodo2, Guy François V Ayissi Eyebe2
1Physics, University of yaounde 1, Yaounde, 812, Cameroon. samueltagne90@yahoo.com.
Scientific Reports
|August 22, 2022
Summary
This study implements a fractional-order chaotic Jerk oscillator on a microcontroller, reducing electronic component needs. The fractional model shows chaotic dynamics unlike its integer counterpart, with potential applications in synchronization.
Area of Science:
- Nonlinear Dynamics
- Chaos Theory
- Microcontroller Systems
Background:
- Traditional chaotic Jerk oscillators require numerous bulky and power-hungry analog components.
- Fractional-order systems offer complex dynamics with potentially simpler hardware implementations.
Purpose of the Study:
- To propose and analyze a fractional-order 3D Chaotic Jerk oscillator implemented on a PIC16F877A microcontroller.
- To reduce the reliance on extensive analog electronic components in chaotic systems.
- To investigate the chaotic behaviors and synchronization capabilities of the fractional model.
Main Methods:
- Analytical, numerical, and experimental analysis of the fractional-order chaotic Jerk oscillator.
- Implementation on a PIC16F877A microcontroller to demonstrate hardware feasibility.
- Study of system dynamics and synchronization under specific initial conditions.
Main Results:
- The fractional-order model exhibits chaotic dynamics for parameter values where the integer-order system shows limit-cycles.
- Successful implementation on a microcontroller reduces hardware complexity and power consumption.
- Synchronization of the chaotic system is demonstrated, highlighting practical applications.
Conclusions:
- Fractional-order chaotic Jerk oscillators can be effectively implemented on microcontrollers, offering a more compact and efficient alternative.
- The fractional model presents richer dynamics compared to its integer-order counterpart.
- The study validates the potential of chaotic systems in synchronization applications through a hardware-realizable approach.
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