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A 4.8 ps root-mean-square resolution time-to-digital converter implemented in a 20 nm Cyclone-10 GX
Xin Yu1, Haojie Xia1, Weishi Li1
1Anhui Province Key Laboratory of Measuring Theory and Precision Instrument, School of Instrument Science and Optoelectronics Engineering, Hefei University of Technology, Hefei 230009, Anhui, China.
The Review of Scientific Instruments
|September 1, 2022
Summary
This study introduces an improved field-programmable gate array (FPGA)-based time-to-digital converter (TDC) for precise time interval measurement. The novel design achieves a 4.8 ps root-mean-square resolution, significantly enhancing measurement accuracy.
Area of Science:
- Electrical Engineering
- Digital Systems Design
- Integrated Circuit Design
Background:
- Improving resolution and precision in field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) for time interval measurement presents significant challenges.
- Existing TDC architectures often face limitations in achieving sub-picosecond accuracy and high precision.
Purpose of the Study:
- To design and implement a high-precision TDC on an FPGA for accurate time interval measurement.
- To overcome the limitations of conventional TDC designs by integrating novel structural and calibration techniques.
Main Methods:
- Designed a carry-look-ahead delay chain structure for enhanced timing resolution.
- Integrated an interleaved sampling method for improved precision.
- Implemented an online calibration and bin readjustment approach for adaptive performance tuning.
- Utilized adaptive logic module units within a Cyclone-10 GX FPGA (20 nm process).
Main Results:
- Achieved a root-mean-square (RMS) resolution of 4.8 picoseconds (ps).
- Obtained a least-significant-bit (LSB) resolution of 5.68 ps.
- Demonstrated superior performance compared to previous TDC implementations.
Conclusions:
- The proposed TDC design, leveraging a carry-look-ahead delay chain and interleaved sampling with online calibration on a low-power FPGA, significantly enhances time interval measurement precision.
- The achieved resolutions (4.8 ps RMS, 5.68 ps LSB) represent a notable advancement in FPGA-based TDC technology.
