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A 4.8 ps root-mean-square resolution time-to-digital converter implemented in a 20 nm Cyclone-10 GX
Xin Yu1, Haojie Xia1, Weishi Li1
1Anhui Province Key Laboratory of Measuring Theory and Precision Instrument, School of Instrument Science and Optoelectronics Engineering, Hefei University of Technology, Hefei 230009, Anhui, China.
Abstract:
It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement. In this study, we design a carry-look-ahead delay chain structure and integrate an interleaved sampling method with an online calibration and bin readjustment approach to implement a TDC. We take advantage of the adaptive logic module units applied in a Cyclone-10 GX (10CX220YF780E5G), which is a 20 nm low-power consumption and low-cost FPGA. In this new generation FPGA, we implemented a high-precision time interval measurement, which exceeded all our previous works with a 4.8 ps root-mean-square resolution and a 5.68 ps least-significant-bit resolution.
