A high-performance two-dimensional transform architecture of variable block sizes for the VVC standard.

Area of Science:

• Digital Signal Processing
• Video Compression Technology
• Hardware Architecture Design

Background:

• The H.266/VVC standard enhances video coding efficiency using tools like Adaptive Multiple Transform (AMT).
• The Discrete Sine Transform-VII (DST-VII) within AMT offers improved coding but introduces computational complexity.
• Optimizing DST-VII computation is crucial for efficient hardware implementation.

Purpose of the Study:

• To propose a unified 2D transform architecture for both exact and approximate DST-VII computation.
• To evaluate the hardware efficiency of an approximate DST-VII implementation for H.266/VVC.
• To demonstrate real-time video coding capabilities with the optimized architecture.

Main Methods:

• Development of a unified 2D transform architecture supporting exact (multipliers, MCM) and approximate (additions, bit-shifting) DST-VII.
• Implementation and synthesis of the proposed designs on an Arria 10 FPGA device.
• Performance analysis focusing on area consumption, logic utilization, and operational speed.

Main Results:

• The approximate DST-VII transform matrices achieved 4% area consumption, reducing logic utilization by over 65% compared to exact multiplier-based designs.
• A 53% hardware cost saving was observed compared to the MCM-based exact computation.
• The approximate-based architecture operates at 78 MHz, enabling real-time 2K (100 fps) and 4K (25 fps) video coding.

Conclusions:

• The proposed approximate DST-VII computation offers a highly efficient hardware solution for H.266/VVC.
• This optimization significantly reduces power consumption, logic resources, and enhances speed.
• The architecture supports real-time video processing for high-resolution content.