A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process.

Area of Science:

• Electrical Engineering
• Biomedical Engineering
• Integrated Circuits

Background:

• Neural stimulators are crucial for therapeutic applications but often require bulky external power sources or complex on-chip voltage generation.
• Existing integrated solutions face challenges in achieving high voltage compliance and efficient power delivery within standard low-voltage CMOS processes.

Purpose of the Study:

• To present a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation.
• To demonstrate the feasibility of implementing HV circuits in a low-voltage CMOS process for neural stimulation.
• To characterize the performance of the integrated neural stimulator, including voltage handling, charge injection, and power efficiency.

Main Methods:

• Design and fabrication of a neural stimulator front-end and a switched-capacitor DC-DC converter in a 180 nm CMOS process.
• Implementation of circuit-level and block-level techniques, including a high-compliance voltage cell, for HV operation.
• Experimental validation using an electrical model of the electrode-tissue interface.

Main Results:

• The integrated neural stimulator successfully generated programmable voltage supplies from 4.2 V to 13.2 V.
• It delivered stimulation currents up to 2.08 mA with 5 bits resolution and handled voltage supplies up to 4 times the technology's nominal supply.
• Residual charge was below 0.12%, and an overall power efficiency of 48% was achieved at maximum stimulation current.

Conclusions:

• A fully integrated HV neural stimulator capable of operating in standard low-voltage CMOS processes was successfully demonstrated.
• The proposed design enables high-performance neural stimulation with efficient on-chip power generation.
• This work paves the way for more compact and efficient implantable neural stimulation systems.