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Metal-Semiconductor Junctions

Metal-Semiconductor Junctions

The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
Schottky Barriers
Schottky barriers arise when a metal with a work function (Φm) contacts a semiconductor with a different work function (Φs). Initially, electrons transfer until the Fermi levels of the metal and semiconductor align at equilibrium. For instance, if Φm > Φs, the semiconductor Fermi level is higher than the metal's before contact. The...

Biasing of Metal-Semiconductor Junctions

Biasing of Metal-Semiconductor Junctions

Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...

P-N junction

P-N junction

A p-n junction is formed when p-type and n-type semiconductor materials are joined together. At the interface of the p-n junction, holes from the p-side and electrons from the n-side begin to diffuse into the opposite sides due to the concentration gradient. This diffusion of carriers leads to a region around the junction where there are no free charge carriers, known as the depletion region. The charge density within the depletion region for the n-side and p-side can be described by the...

Biasing of FET

Biasing of FET

Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the...

Biasing of P-N Junction

Biasing of P-N Junction

The operation of a p-n junction diode involves various biasing conditions, including forward bias, reverse bias, and equilibrium.
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...

Schottky Barrier Diode

Schottky Barrier Diode

Schottky barrier diodes are specialized semiconductor devices characterized by their unique construction. This construction involves combining a metal layer with a moderately doped n-type semiconductor material. This combination leads to the formation of a Schottky barrier, a pivotal element that defines the diode's operational characteristics. The core functionality of Schottky barrier diodes is their capacity to allow current to flow in only one direction due to their distinctive...

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Related Experiment Video

Updated: Aug 28, 2025

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

Dual-gated mono-bilayer graphene junctions.

Mingde Du¹, Luojun Du¹, Nan Wei²

¹Department of Electronics and Nanoengineering, Aalto University Espoo FI-02150 Finland mingde.du@aalto.fi.

Nanoscale Advances

|September 22, 2022

Summary

Researchers created an electrically tunable lateral junction using dual-gated graphene. This breakthrough in graphene electronics shows a significant, gate-controlled conductance difference, paving the way for advanced electronic devices.

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Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

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Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

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Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

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Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Published on: July 24, 2015

Area of Science:

Materials Science
Condensed Matter Physics
Nanotechnology

Background:

Atomically sharp lateral junctions are crucial for advanced electronics, photonics, and optoelectronics.
Graphene's unique electronic properties make it a promising material for next-generation electronic components.

Purpose of the Study:

To demonstrate an electrically tunable lateral junction at atomically sharp interfaces between dual-gated monolayer and bilayer graphene.
To investigate the transport properties and gate-tunable behavior of this novel graphene interface.

Main Methods:

Systematic investigation of transport properties using source-drain voltage (Ids-Vds) and transfer curves.
Measurement of Ids-Vds curves with bias voltage applied in opposite directions across the asymmetric interface.
Simulation of Ids-Vds curves using a new numerical model.

Main Results:

Observed nearly 30% difference in output Ids-Vds curves measured at opposite bias directions.
Demonstrated that conductance difference is highly dependent on doping levels controlled by dual-gating.
Confirmed the existence of a gate-tunable junction due to differing band structures of monolayer and bilayer graphene.

Conclusions:

The dual-gated mono-bilayer graphene junction exhibits electrically tunable characteristics.
A new numerical simulation protocol validates the junction's behavior.
This work offers a potential pathway for functional applications of graphene in next-generation electronics.