Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking

Area of Science:

• Cybersecurity and Hardware Security
• Integrated Circuit Design and Analysis

Background:

• Hardware masking is crucial for protecting integrated circuits, but practical designs often violate share independence assumptions.
• Noise coupling between masking shares in VLSI circuits leads to information leakage, which is challenging to model and mitigate.
• Existing countermeasures struggle with sophisticated interactions in modern circuits, necessitating novel approaches to secure power delivery.

Purpose of the Study:

• To investigate the effectiveness of on-chip voltage regulators in minimizing noise coupling among hardware masking shares.
• To explore various voltage regulator configurations and their impact on the shared power delivery network (PDN) security.
• To analyze the influence of voltage regulator placement and PDN impedance on information leakage between masking shares.

Main Methods:

• Simulated a power delivery network (PDN) with two masking shares using different voltage regulator configurations (ideal, DLDOs, phase-shifted DLDOs).
• Evaluated PDN impedance effects on security using an 18x18 grid with a normal DLDO.
• Performed security analysis via correlation and t-test metrics, with t-test values below 4.5 indicating negligible coupling.

Main Results:

• On-chip voltage regulator placement significantly impacts coupling between masking shares.
• Certain configurations, such as dual DLDOs with a 180° phase shift, achieved satisfactory security levels (t-test < 4.5).
• Achieved up to an 80% reduction in correlation between masking shares, demonstrating improved security.

Conclusions:

• Utilizing on-chip voltage regulators, particularly dual DLDOs with phase shifting, is an effective countermeasure against noise coupling in hardware masking.
• Optimizing voltage regulator placement closer to masking shares further enhances PDN security.
• The proposed techniques offer a viable solution for mitigating information leakage in masked hardware implementations.