A steep switching WSe₂ impact ionization field-effect transistor

Area of Science:

• Materials Science
• Semiconductor Physics
• Device Engineering

Background:

• Fermi-Dirac carrier distribution and drift-diffusion transport limit subthreshold slope (SS) in field-effect transistors (FETs).
• Reducing SS is crucial for optimizing energy consumption in electronic devices.

Purpose of the Study:

• To realize steep-slope impact ionization field-effect transistors (I²FETs) overcoming SS limitations.
• To investigate the carrier transport mechanisms in WSe₂ for low SS devices.
• To demonstrate the functionality of I²FETs in logic circuits.

Main Methods:

• Fabrication of gate-controlled homogeneous WSe₂ lateral junction I²FETs.
• Characterization of device performance including subthreshold slope and on/off ratio at room temperature and low bias.
• Investigation of carrier transport mechanisms, specifically the lucky-drift mechanism.
• Construction and testing of a logic inverter using a WSe₂ I²FET and a MoS₂ FET.

Main Results:

• Achieved average SS down to 2.73 mV/dec over three decades of source-drain current.
• Demonstrated an on/off ratio of approximately 10⁶ at room temperature and low bias (<1 V).
• Confirmed the validity of the lucky-drift mechanism in WSe₂, enabling high impact ionization coefficients and low SS.
• Fabricated a logic inverter with a gain of 73 and near-ideal noise margins.

Conclusions:

• WSe₂ I²FETs offer a promising route to overcome fundamental barriers in FET design.
• The demonstrated devices exhibit excellent performance for energy-efficient electronic applications.
• This work provides a foundation for the development of next-generation low-power electronic devices.