An Efficient Model-Compressed EEGNet Accelerator for Generalized Brain-Computer Interfaces With Near Sensor...

Area of Science:

• * Neuroscience
• * Computer Engineering
• * Signal Processing

Background:

• * Brain-computer interfaces (BCIs) leverage electroencephalogram (EEG) signals for machine interaction.
• * EEGNet, a compact neural network for BCIs, faces efficiency challenges in hardware implementations.
• * Low-power, long-term operation is crucial for wearable BCI devices.

Purpose of the Study:

• * To propose an efficient EEGNet inference accelerator for low-power wearable BCI devices.
• * To optimize EEGNet through model compression techniques.
• * To design a hardware accelerator minimizing area and power consumption.

Main Methods:

• * EEGNet model compression using embedded channel selection, normalization merging, and product quantization.
• * Customized accelerator design with reused multiply-accumulators and processing elements (PEs).
• * PE clock-gating for power saving and weight/intermediate result quantization for memory reduction.

Main Results:

• * FPGA experiments demonstrate good generalization across three BCI datasets.
• * The design achieves significant reductions in area (3.31%) and power (1.35%) compared to parallel designs.
• * Embedded channel selection provides speedups of 1.4-3.7 with negligible accuracy loss (-0.80%).
• * CMOS synthesis shows 87.22% area and 20.77% energy efficiency improvements over RISC-V MCU implementation.

Conclusions:

• * The proposed efficient EEGNet accelerator enables practical, low-power, long-term BCI applications.
• * Model compression and hardware optimization are key to achieving high efficiency in wearable devices.
• * The design offers a significant advancement for real-time EEG signal processing in BCIs.