A Fully Integrated Low-Dropout Regulator with Improved Load Regulation and Transient Responses

Area of Science:

• Electrical Engineering
• Integrated Circuit Design

Background:

• Low-dropout (LDO) regulators are crucial power management components in integrated circuits.
• Existing LDO designs often face trade-offs between load regulation, transient response, and quiescent current consumption.
• The need for high-performance LDOs in advanced semiconductor technologies (e.g., 40 nm) is increasing.

Purpose of the Study:

• To develop a fully integrated LDO regulator with enhanced load regulation and transient response characteristics.
• To maintain stable operation across a wide range of load currents (0-100 mA) in a 40 nm technology node.
• To achieve a good figure of merit (FOM) without requiring additional transient enhancement circuits.

Main Methods:

• Implementation of a three-stage structure combining an adjustable threshold push-pull stage (ATPS) and master-slave power transistors.
• Utilizing the ATPS with an adjustable turn-on threshold controlled by a current source for efficient light-load operation.
• Analysis of stability with varying parasitic load capacitance (up to 100 pF) and compensation capacitor (0.7 pF).

Main Results:

• Achieved a superior load regulation of 0.017 mV/mA.
• Demonstrated stability from 0 to 100 mA load current.
• Transient response showed undershoot and overshoot less than 33 mV for a 100 mA load transient with a 100 ns edge time.
• Dropout voltage was 200 mV at a 1.1 V input voltage.
• No-load current consumption was 24.6 μA.

Conclusions:

• The proposed LDO regulator design effectively improves load regulation and transient responses in 40 nm technology.
• The integrated ATPS and master-slave topology provide stable performance across the full load range with low quiescent current.
• The design offers a good FOM and meets stringent performance requirements without external components for transient enhancement.