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A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform.

Meng Sha1,2, Zhichuan Guo1,2, Yunfei Guo1,2

  • 1National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China.

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Summary

This research introduces a novel architecture for accelerating Software-Defined Networking (SDN) using a Multi-Processor System-on-Chip (MPSoC) platform. The proposed design enhances network flexibility and achieves high performance at 100 Gbps by localizing control decisions.

Keywords:
FPGASDNnetwork accelerationreprogrammable hardware

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Area of Science:

  • Computer Engineering
  • Network Architecture
  • High-Speed Networking

Background:

  • Software-Defined Networking (SDN) separates control and data planes for flexibility, often using software for data plane implementation.
  • Increasing network speeds challenge CPU capabilities for high-speed packet processing.
  • Current FPGA-based acceleration centralizes intelligence remotely, increasing controller-switch latency.

Purpose of the Study:

  • To propose a novel, high-performance, and flexible architecture for accelerating SDN.
  • To address the latency issues associated with centralized control in high-speed networks.
  • To leverage Multi-Processor System-on-Chip (MPSoC) platforms for localized control decisions.

Main Methods:

  • Implemented a novel architecture on an MPSoC platform, with the control plane on-chip CPU and the data plane in FPGA logic.
  • Utilized Ethernet for communication between the CPU and FPGA.
  • Designed a high-performance Ternary Content-Addressable Memory (TCAM) using distributed RAM.
  • Employed a pipeline design with modules connected via the AXI Stream interface.

Main Results:

  • Achieved high performance at 100 Gbps for the proposed SDN acceleration architecture.
  • Demonstrated flexibility to support multiple network functions.
  • Successfully integrated control plane intelligence locally on the MPSoC platform.

Conclusions:

  • The proposed MPSoC-based architecture effectively accelerates SDN with high performance and flexibility.
  • Localizing control decisions within the network edge significantly reduces latency.
  • This represents a novel approach to 100 Gbps SDN system design.