A Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures

Area of Science:

• Computer Architecture
• Performance Optimization
• Cache Memory Management

Background:

• Asymmetric multi-core architectures feature heterogeneous cores sharing the last-level cache (LLC).
• Diverse memory access patterns of heterogeneous cores intensify LLC competition and interference.
• Existing cache replacement policies struggle to efficiently manage shared LLCs in heterogeneous systems.

Purpose of the Study:

• To propose a heterogeneity-aware replacement policy for partitioned caches (HAPC).
• To reduce mutual interference between heterogeneous cores in shared LLC environments.
• To enhance LLC access efficiency, particularly for performance-critical big cores.

Main Methods:

• Implemented cache partitioning to isolate core interference.
• Developed runtime tracking of shared cache block reuse states within partitions.
• Designed HAPC to prioritize cache blocks utilized by big cores based on memory access differences.

Main Results:

• HAPC significantly improves the performance of big cores in multithreaded programs.
• The impact on little cores is minimal, maintaining their performance levels.
• Overall system performance is enhanced due to improved LLC access efficiency.

Conclusions:

• HAPC effectively addresses LLC contention in asymmetric multi-core systems.
• The policy's heterogeneity-aware approach optimizes cache utilization for diverse core types.
• HAPC offers a superior alternative to LRU and SRCP for improving system performance.