A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges...

Area of Science:

• Computer Science
• Electrical Engineering
• Artificial Intelligence

Background:

• Graph Convolutional Networks (GCNs) excel at extracting representations from graph data for applications like recommendation systems and NLP.
• GCN inference demands low latency and high energy efficiency, posing challenges for deployment in critical applications.
• Field-Programmable Gate Arrays (FPGAs) offer a promising hardware acceleration platform for GCNs, balancing performance and power.

Purpose of the Study:

• To systematically review and categorize the challenges in designing FPGA-based GCN accelerators.
• To survey existing FPGA-based GCN accelerator designs and their solutions to identified challenges.
• To provide a comparative analysis of current accelerators based on resource utilization, performance, and power consumption.

Main Methods:

• Summarized four key challenges in FPGA-based GCN accelerator design.
• Introduced typical Graph Neural Network (GNN) algorithms and representative GCN models.
• Reviewed recent FPGA-based GCN accelerators, detailing their design strategies for specific challenges.
• Compared performance metrics, resource usage, and power consumption of various accelerators.

Main Results:

• Identified and categorized major challenges in FPGA-based GCN acceleration.
• Presented a comprehensive overview of state-of-the-art FPGA accelerators for GCNs.
• Provided a comparative analysis of existing solutions, highlighting trade-offs in performance, resources, and power.

Conclusions:

• FPGA accelerators are crucial for efficient GCN inference, but customization presents significant challenges.
• Future research should focus on algorithm-hardware co-design, efficient task scheduling, enhanced generality, and accelerated development cycles for FPGA-based GCNs.