Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect.

Area of Science:

• Computer Engineering
• VLSI Design
• Network Architecture

Background:

• Networks-on-Chip (NoCs) are essential for multi/manycore systems.
• Traditional NoC routers use buffers that are power-intensive and often underutilized.
• Non-uniform traffic patterns in applications degrade performance due to buffer inefficiency.

Purpose of the Study:

• To introduce and evaluate the Roundabout NoC (R-NoC) concept for improved buffer utilization and performance.
• To explore novel R-NoC configurations leveraging its distributed internal routing.
• To assess the performance and power efficiency of R-NoC implementations on 45 nm CMOS technology.

Main Methods:

• Inspired by traffic roundabouts, R-NoC uses shared lanes for multiple ports to maximize buffer utilization.
• Employs router-internal adaptive routing based on back pressure signals for efficient packet routing.
• Utilizes elastic buffers for control flow, enabling handshaking similar to asynchronous circuits.
• Investigates novel R-NoC configurations and evaluates them on 45 nm CMOS technology.

Main Results:

• R-NoC configurations demonstrate significant performance improvements over standard mesh and input-buffered routers.
• Buffer resource utilization is maximized, leading to better performance for non-uniform traffic.
• Area and power consumption are not compromised compared to traditional designs.
• A diagonally-linked R-NoC configuration offers enhanced performance and energy efficiency with moderate area overhead.

Conclusions:

• R-NoC provides a promising solution for enhancing NoC performance and energy efficiency.
• The distributed nature of R-NoC allows for flexible and optimized router configurations.
• R-NoC effectively addresses the challenges of buffer underutilization and performance degradation in multi/manycore systems.