Process Optimization and Performance Evaluation of TSV Arrays for High Voltage Application.

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Manufacturing

Background:

• High-quality through-silicon via (TSV) arrays are crucial for high voltage applications.
• Existing fabrication methods face challenges in achieving desired structural integrity and electrical performance.

Purpose of the Study:

• To optimize the fabrication process for high-quality TSV arrays suitable for high voltage applications.
• To evaluate dielectric layers, copper plating, and the final electrical properties of the TSVs.

Main Methods:

• Fabrication of Si through-holes using deep reactive etching (DRIE) and backside grinding.
• Sidewall smoothing via thermal oxidation and wet etching.
• Dielectric layer evaluation using a test kit.
• Bottom-up copper electroplating and annealing for hole filling.
• Structural and electrical characterization using SEM, EDX, and leakage current measurements.

Main Results:

• Optimized DRIE process reduced top scallop width to 540 nm.
• Smoothed sidewalls and defect-free TSV arrays observed via SEM.
• No detectable interdiffusion between copper and dielectric layers shown by EDX.
• Achieved extremely low leakage currents (6.80 × 10^-10 A at 350 V ramp, 2.86 × 10^-9 A at 100 V sustained).

Conclusions:

• The optimized fabrication process successfully produced high-quality TSV arrays for high voltage applications.
• The developed TSVs exhibit excellent structural integrity and superior electrical insulation properties.
• This work provides a viable method for manufacturing reliable TSVs for demanding electronic systems.