Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural...

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• Hardware implementation of neural networks (NNs) faces challenges in memory element and array requirements for complex tasks.
• Current architectures increase chip size and memory array needs for distinct feature extraction and classification operations.

Purpose of the Study:

• To propose a novel three-dimensional ferroelectric NAND (3D FeNAND) array architecture.
• To achieve area-efficient hardware implementation of neural networks (NNs).

Main Methods:

• Development and integration of a three-dimensional ferroelectric NAND (3D FeNAND) array.
• Demonstration of vector-matrix multiplication using the integrated 3D FeNAND arrays.
• Allocation of vertical layers within the 3D FeNAND as hidden layers for NN tasks.

Main Results:

• Successful demonstration of vector-matrix multiplication.
• Achieved excellent pattern classification, including color-mixed patterns.
• Enabled different tasks to be performed at distinct vertical layers within the 3D FeNAND array.

Conclusions:

• The proposed 3D FeNAND array offers a practical strategy for high-performance and efficient NN systems.
• Vertical stacking of computation components addresses area-efficiency challenges in hardware NNs.
• This approach facilitates the realization of complex NN models in a compact hardware form factor.