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Residual stress modulation as a pathway to reliable multilevel 3D NAND flash storage
Ruifu Zhou1, Ik-Jyae Kim1, Sejun Park2
1Pohang University of Science and Technology (POSTECH) Pohang 37673 Korea jangsik@postech.ac.kr.
Nanoscale Advances
|June 1, 2026
Summary
Residual stress in 3D NAND flash memory impacts reliability. A new stress engineering layer (SEL) increases compressive stress in the charge-trap nitride (CTN) layer, improving data retention and device reliability.
Area of Science:
- Semiconductor device physics
- Materials science
- Electrical engineering
Background:
- Three-dimensional (3D) NAND flash memory utilizes vertical stacking for high density.
- Increased layer stacking in 3D NAND generates residual stress, degrading structural integrity and electrical performance.
- Managing residual stress is crucial for 3D NAND device reliability.
Purpose of the Study:
- To investigate the impact of residual stress on charge-trap 3D NAND reliability using simulation.
- To propose and evaluate a novel stress engineering layer (SEL) for mitigating stress-induced degradation.
Main Methods:
- Sentaurus technology computer-aided design (TCAD) simulations were employed.
- The study analyzed the effect of residual stress on charge-trap nitride (CTN) layer properties.
- A stress engineering layer (SEL) was simulated between the poly-Si channel and oxide filler.
Main Results:
- Increased compressive stress in the CTN layer was shown to enhance data retention via band-edge modulation.
- The proposed SEL effectively increased compressive stress within the CTN layer.
- The SEL technique demonstrated a reduction in retention degradation.
Conclusions:
- Residual stress significantly influences 3D NAND reliability.
- The proposed SEL is a viable method for modulating residual stress.
- Implementing the SEL can improve the overall reliability of 3D NAND flash memory devices.
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