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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Structure Optimization of Planar Nanoscale Vacuum Channel Transistor
Ji Xu1, Congyuan Lin1, Yu Li1
1School of Electronic and Information Engineering, Nanjing University of Information Science and Technology, Nanjing 210044, China.
Researchers simulated and fabricated nanoscale vacuum channel transistors (NVCTs), demonstrating their potential for high integration in novel vacuum nanoelectronics by optimizing emitter tip morphology for improved performance.
Area of Science:
- Solid State Physics
- Nanoelectronics
- Materials Science
Background:
- Nanoscale vacuum channel transistors (NVCTs) represent a novel advancement in vacuum nanoelectronics.
- Their unique structure offers potential for high-performance electronic devices.
Purpose of the Study:
- To simulate and analyze the structural parameters of planar-type NVCTs.
- To investigate the influence of emitter tip morphology on the emission performance of NVCTs.
- To fabricate and characterize back-gate and side-gate NVCTs.
Main Methods:
- Finite element simulations were employed to model NVCT structural parameters.
- Emitter tip morphology was systematically varied in simulations.
- Back-gate and side-gate NVCTs were fabricated based on simulation insights.
- Electrical properties of the fabricated NVCTs were experimentally investigated.
Main Results:
- Simulation results revealed a significant impact of emitter tip morphology on emission performance.
- Successful fabrication of both back-gate and side-gate NVCT configurations was achieved.
- Experimental characterization demonstrated the functional electric properties of the fabricated NVCTs.
Conclusions:
- Optimizing emitter tip morphology is crucial for enhancing NVCT performance.
- The fabrication and characterization of NVCTs show promise for high integration.
- NVCTs hold potential for next-generation electronic devices with superior characteristics.
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