A Low-Power Hardware Architecture for Real-Time CNN Computing.

Area of Science:

• Edge computing
• Hardware acceleration
• Deep learning

Background:

• Convolutional Neural Networks (CNNs) are essential for edge AI tasks but are computationally intensive.
• Limited resources and power constraints on edge devices challenge CNN deployment.
• Real-time computing (RTC) systems require balancing computational latency and power consumption.

Purpose of the Study:

• To propose a low-power CNN accelerator for edge inference in RTC systems.
• To address the trade-off between computational latency and power consumption for edge AI.
• To reduce hardware resource and power consumption for CNN operations.

Main Methods:

• Column-wise computation for immediate processing of input data.
• A multi-cycle scheme for column-wise convolutional operations to reduce resource and power usage.
• Implementation of a domain-specific CNN architecture in 65 nm technology.

Main Results:

• Achieved significant power reductions: 8.45% for LeNet, 49.41% for AlexNet, and 50.64% for VGG16.
• The proposed approach demonstrates greater power reduction for deeper CNN models with larger kernels and more channels.
• Validated the effectiveness of the multi-cycle scheme on hardware.

Conclusions:

• The developed low-power CNN accelerator effectively reduces power consumption for edge inference in RTC systems.
• The multi-cycle scheme is a viable strategy for optimizing CNN hardware for resource-constrained environments.
• The approach shows promise for deploying complex CNN models on power-sensitive edge devices.