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Summary

This summary is machine-generated.

This study introduces new metrics to evaluate pattern set coverage for optical proximity correction (OPC) models. These metrics improve model accuracy and reduce costs associated with integrated circuit (IC) chip design and manufacturing.

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Area of Science:

Semiconductor manufacturing
Integrated circuit (IC) design
Lithography and patterning

Background:

Accurate optical proximity correction (OPC) modeling is crucial for advanced semiconductor technology nodes, impacting integrated circuit (IC) chip mask tape-out, yield, and time-to-market.
Current OPC model calibration relies on pattern sets, but lacks effective metrics to assess coverage sufficiency before mask tape-out, leading to potential delays and increased costs.
Large pattern variety in full chip layouts necessitates an optimal pattern set for effective model calibration.

Purpose of the Study:

To develop novel metrics for evaluating pattern coverage in OPC model calibration prior to metrology data acquisition.
To enhance the efficiency and accuracy of OPC model building for semiconductor manufacturing.
To reduce the risks of costly re-tape outs and product launch delays caused by insufficient pattern set coverage.

Main Methods:

Constructed pattern coverage evaluation metrics based on intrinsic numerical feature representation.
Utilized potential model simulation behavior to develop coverage metrics.
Proposed an incremental pattern selection method based on simulation error.

Main Results:

Demonstrated a positive correlation between the developed metrics and lithographic model accuracy through experimental validation.
The incremental selection method reduced the model's verification error range by up to 53%.
The proposed methods improve the efficiency of OPC model building and overall OPC recipe development.

Conclusions:

The developed pattern coverage evaluation metrics provide a proactive approach to ensure optimal pattern set selection for OPC model calibration.
These metrics significantly enhance the efficiency of OPC model building, leading to reduced costs and faster time-to-market for integrated circuits.
The findings contribute to improving the robustness and reliability of the entire OPC recipe development process in advanced semiconductor manufacturing.