Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using...

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Materials Science

Background:

• Processing-in-Memory (PIM) architectures are crucial for accelerating artificial neural networks (ANNs).
• Resistive Random Access Memory (RRAM) offers promising characteristics for PIM applications due to its non-volatility and high density.
• Existing RRAM PIM designs often require Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), increasing power consumption and complexity.

Purpose of the Study:

• To propose a novel RRAM PIM accelerator architecture for ANNs.
• To eliminate the need for ADCs and DACs in RRAM PIM systems.
• To minimize data transportation and power consumption in convolution computations.

Main Methods:

• Developed an RRAM PIM accelerator architecture.
• Implemented partial quantization to mitigate accuracy loss.
• Avoided additional memory usage to reduce data movement.

Main Results:

• The proposed RRAM PIM architecture achieves an image recognition rate of 284 frames per second at 50 MHz for Convolutional Neural Network (CNN) algorithms.
• The architecture significantly reduces overall power consumption and accelerates computation.
• Partial quantization minimally impacts accuracy compared to non-quantized algorithms.

Conclusions:

• The developed RRAM PIM accelerator offers an efficient and high-performance solution for ANNs.
• Eliminating ADCs/DACs and minimizing data movement are key to achieving substantial power savings and speedups.
• The architecture demonstrates the potential of RRAM-based PIM for next-generation AI hardware.