An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM...

Area of Science:

• Neuromorphic Engineering
• Artificial Intelligence Hardware
• Integrated Circuit Design

Background:

• Spiking Neural Networks (SNNs) offer energy-efficient computation but require specialized hardware for on-chip learning.
• Processing-in-Memory (PIM) architectures aim to reduce data movement bottlenecks by performing computation within memory arrays.
• Spike-Time-Dependent Plasticity (STDP) is a biologically inspired unsupervised learning rule crucial for SNNs.

Purpose of the Study:

• To develop a hardware-friendly SNN architecture integrated with SRAM PIM for efficient on-chip unsupervised learning.
• To co-design algorithms and hardware for improved area and energy efficiency in SNNs utilizing STDP.
• To demonstrate the feasibility of the proposed architecture for real-world pattern recognition tasks like MNIST dataset.

Main Methods:

• Implementation of a novel SRAM PIM macro supporting parallel Reconfigurable Multi-bit PIM Multiply-Accumulate (RMPMA) operations.
• Design of a high-precision PIM Threshold Generator (PHPTG) for accurate neuron behavior.
• Integration of a simplified Winner Takes All (WTA) mechanism and a hardware-friendly STDP algorithm for unsupervised learning.

Main Results:

• The fabricated chip achieved a low learning efficiency of 0.47 nJ/pixel.
• Demonstrated a remarkable learning energy efficiency of 70.38 TOPS/W.
• Successfully recognized the Modified National Institute of Standards and Technology (MNIST) dataset through on-chip unsupervised learning.

Conclusions:

• The proposed SRAM PIM-based SNN with on-chip STDP learning offers a significant advancement in energy and area efficiency.
• This work validates the co-design approach for hardware-friendly SNNs and efficient learning methodologies.
• The developed architecture provides a promising pathway for low-power, resource-efficient on-chip learning systems.