A 5.3 pJ/Spike CMOS Neural Array Employing Time-Modulated Axon-Sharing and Background Mismatch Calibration Techniques

Inspired by the human brain, spiking neuron networks are promising to realize energy-efficient and low-latency neuromorphic computing. However, even state-of-the-art silicon neurons are orders of magnitude worse than biological neurons in terms of area and power consumption due to the limitations. Moreover, limited routing in typical CMOS processes is another challenge for realizing the fully-parallel high-throughput synapse connections compared to biological synapses. This paper presents an SNN circuit that utilizes resource-sharing techniques to address the two challenges. Firstly, a comparator sharing neuron circuit with a background calibration technique is proposed to shrink the size of a single neuron without performance degradation. Secondly, a time-modulated axon-sharing synapse system is proposed to realize a fully-parallel connection with limited hardware overhead. To validate the proposed approaches, a CMOS neuron array is designed and fabricated under a 55-nm process. It consists of 48 LIF neurons with 3125 neurons/mm area density, power consumption of 5.3 pJ/spike, and equivalent 2304 fully parallel synapses providing a unit throughput of 5500 events/s/neuron. It proves the proposed approaches are promising to realize a high-throughput high-efficiency SNN with CMOS technology.