Robustness and reproducibility of simple and complex synthetic logic circuit designs using a DBTL loop

Area of Science:

• Synthetic biology
• Computational biology
• Genetic engineering

Background:

• Existing computational tools for synthetic genetic network design-build-test-learn (DBTL) loops are fragmented.
• A comprehensive, integrated approach is needed to streamline the entire DBTL cycle.

Purpose of the Study:

• To introduce Design Assemble Round Trip (DART), an end-to-end computational toolchain for synthetic genetic network construction.
• To enhance the design and assembly phases of the DBTL loop, focusing on rational selection and robust performance screening.
• To provide computational support for the experimental process, data management, and analysis.

Main Methods:

• Developed the Design Assemble (DA) component of DART to screen thousands of network topologies using a novel robustness score based on circuit topology and dynamical behavior.
• Integrated DA with the existing Round Trip (RT) test-learn loop for experimental support, metadata management, and data analysis.
• Implemented DART for designing and testing OR and NOR genetic circuits in budding yeast, including analysis of structural redundancy.
• Applied machine learning techniques for segmenting bimodal flow cytometry distributions in data analysis.

Main Results:

• DART successfully facilitated a complete design-through-analysis sequence for synthetic genetic circuits.
• The toolchain demonstrated rational selection and refinement of genetic parts for circuit construction.
• Screening identified network topologies with robust and reproducible performance across different experimental conditions.
• Analysis revealed that increased circuit complexity can enhance robustness and reproducibility.

Conclusions:

• DART offers a comprehensive solution for the DBTL loop in synthetic biology.
• The toolchain enables efficient screening of genetic network designs for improved robustness.
• Experimental validation confirmed the predictive power of DART for synthetic circuit performance.
• Findings suggest a trade-off between circuit complexity and performance robustness.