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A Fast and Low-Power Detection System for the Missing Pin Chip Based on YOLOv4-Tiny Algorithm.

Shiyi Chen1, Wugang Lai1, Junjie Ye2

  • 1School of Mechanical and Electrical Engineering, Chengdu University of Technology, Chengdu 610059, China.

Sensors (Basel, Switzerland)
|April 28, 2023
PubMed
Summary
This summary is machine-generated.

This study introduces a fast, low-power system for detecting missing chip pins using YOLOv4-tiny and an FPGA. The novel approach significantly improves detection speed and reduces energy consumption for efficient chip quality inspection.

Keywords:
FPGAchip detectioninference acceleratorlow-power system

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Area of Science:

  • Computer Vision
  • Hardware Acceleration
  • Semiconductor Manufacturing

Background:

  • Current chip pin detection methods are inefficient, relying on manual inspection or power-hungry single-chip systems.
  • Existing machine vision algorithms lack speed and power efficiency for large-scale chip quality control.

Purpose of the Study:

  • To develop a fast and low-power multi-object detection system for identifying missing chip pins.
  • To leverage the YOLOv4-tiny algorithm and FPGA hardware acceleration for improved chip inspection.

Main Methods:

  • Implemented a multi-object detection system using YOLOv4-tiny on an AXU2CGB FPGA platform.
  • Utilized loop tiling, ping-pong optimization, and parallel convolution kernels for hardware acceleration.
  • Enhanced the dataset and optimized network parameters for improved accuracy and efficiency.

Main Results:

  • Achieved a detection speed of 0.468 seconds per image with 3.52 W power consumption.
  • Obtained 89.33% mean average precision (mAP) and a 100% missing pin recognition rate.
  • Reduced detection time by 73.27% and power consumption by 23.08% compared to CPU-based methods.

Conclusions:

  • The proposed system offers a significant improvement in speed and power efficiency for chip pin defect detection.
  • This low-power, high-performance solution is suitable for real-time, large-scale chip quality inspection.
  • The integration of YOLOv4-tiny with FPGA acceleration provides a balanced performance boost over existing solutions.