An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method.

Area of Science:

• Artificial Intelligence
• Computer Engineering
• Hardware Acceleration

Background:

• Bayesian neural networks (BNNs) offer robustness for safety-critical applications.
• BNN inference is computationally intensive, hindering deployment on low-power or embedded systems.
• Existing methods for uncertainty evaluation in BNNs are resource-demanding.

Purpose of the Study:

• To optimize the hardware performance of BNN inference using stochastic computing (SC).
• To reduce energy consumption and improve hardware utilization for BNNs.
• To enable BNN deployment in resource-constrained environments.

Main Methods:

• Proposed an SC approach for BNN inference, utilizing bitstreams for Gaussian random numbers.
• Simplified Gaussian random number generation by omitting complex CLT-based GRNG computations.
• Replaced multipliers with AND operations and employed asynchronous parallel pipeline techniques.
• Implemented the SC-based BNN (StocBNN) on an FPGA.

Main Results:

• The StocBNN achieved significantly lower energy consumption and hardware resource utilization compared to conventional BNNs.
• The FPGA implementation with a 128-bit bitstream demonstrated substantial efficiency gains.
• Accuracy remained high, with less than a 0.1% decrease on MNIST/Fashion-MNIST datasets.

Conclusions:

• Stochastic computing offers an effective method for accelerating BNN inference on hardware.
• The proposed StocBNN design provides a viable solution for energy-efficient BNN deployment.
• This approach paves the way for robust AI in low-power and embedded systems.