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Performance aware shared memory hierarchy model for multicore processors
Ahmed M Mohamed1, Nada Mubark2, Saad Zagloul3
1Electrical Engineering Department, Faculty of Engineering, Aswan University, Aswan, Egypt. amohamed@aswu.edu.eg.
Scientific Reports
|May 5, 2023
Summary
This study models shared hierarchical memory systems in multicore processors. The analytical model evaluates memory response time and access time variance, crucial for optimizing performance.
Area of Science:
- Computer Architecture
- Performance Analysis
- Memory Systems
Background:
- Multicore and many-core processors offer improved speed and efficiency but present memory management challenges.
- The increasing speed gap between processors and memory necessitates advanced performance modeling.
- Shared hierarchical memory systems are critical components in modern multicore architectures.
Purpose of the Study:
- To analytically model the behavior of shared hierarchical memory systems.
- To evaluate the response time and access time variance within these systems.
- To identify key factors affecting hierarchical memory system performance in multicore processors.
Main Methods:
- Development of an analytical model for shared hierarchical memory systems.
- Inclusion of interdependencies between different memory layers.
- Differentiation between memory response time and memory system time.
- Evaluation of the impact of memory hierarchy on memory access time variance.
Main Results:
- The model provides an analytical evaluation of shared hierarchical memory system behavior.
- It quantifies the effect of memory hierarchy on memory access time variance.
- The study highlights how large variance can create performance bottlenecks due to long wait queues.
Conclusions:
- Analytical modeling is essential for understanding and optimizing shared hierarchical memory systems.
- Memory access time variance significantly impacts multicore processor performance.
- The proposed model offers insights into managing memory hierarchy for better system efficiency.
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