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Related Concept Videos

Upsampling01:22

Upsampling

272
Managing signal sampling rates is essential in digital signal processing to maintain signal integrity. A decimated signal, characterized by a reduced frequency range due to its lower sampling rate, can be upsampled by inserting zeros between each sample. This upsampling process expands the original spectrum and introduces repeated spectral replicas at intervals dictated by the new Nyquist frequency. To refine this zero-inserted sequence, it is passed through a lowpass filter with a cutoff...
272
Downsampling01:20

Downsampling

202
When considering a sampled sequence with zero values between sampling instants, one can replace it by taking every N-th value of the sequence. At these integer multiples of N, the original and sampled sequences coincide. This process, known as decimation, involves extracting every N-th sample from a sequence, thereby creating a more efficient sequence.
The Fourier transform of the decimated sequence reveals a combination of scaled and shifted versions of the original spectrum. This...
202
Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

850
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
850
Sampling Continuous Time Signal01:11

Sampling Continuous Time Signal

297
In signal processing, a continuous-time signal can be sampled using an impulse-train sampling technique, followed by the zero-order hold method. Impulse-train sampling involves the use of a periodic impulse train, which consists of a series of delta functions spaced at regular intervals determined by the sampling period. When a continuous-time signal is multiplied by this impulse train, it generates impulses with amplitudes corresponding to the signal's values at the sampling points.
In the...
297
MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

402
Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
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Voltage Doubler Circuit01:23

Voltage Doubler Circuit

696
A voltage doubler circuit integrates two main components: a clamping section and a rectifier section. The clamping section consists of a capacitor (C1) and a diode (D1), whereas the rectifier section is equipped with another diode (D2) and capacitor (C2). This circuit produces an output voltage with twice the amplitude of the sinusoidal input voltage.
696

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An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor.

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Summary

This study introduces a novel one-channel read-out circuit for lateral overflow integration capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensors. This design efficiently processes both high-conversion-gain (HCG) and low-conversion-gain (LCG) signals, reducing area by half.

Keywords:
CMOS image sensorHDRLOFICdouble-samplingread-out chainsmall area

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Area of Science:

  • Electrical Engineering
  • Semiconductor Devices
  • Image Sensors

Background:

  • Lateral Overflow Integration Capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensors enable high-dynamic-range (HDR) imaging by combining low-conversion-gain (LCG) and high-conversion-gain (HCG) signals.
  • Conventional LOFIC-CMOS sensors require a two-channel read-out chain for inverted polarity LCG and HCG signals, increasing chip area.

Purpose of the Study:

  • To develop an area-efficient LOFIC-CMOS image sensor by presenting a single-channel read-out circuit.
  • To enable processing of both HCG and LCG signals within a single read-out chain.

Main Methods:

  • Designed an up/down double-sampling circuit incorporating an inverting amplifier for HCG signals and a non-inverting attenuator for LCG signals.
  • Fabricated a test chip using a 0.18 μm CMOS process with a metal-insulator-metal (MIM) capacitor.

Main Results:

  • Achieved a readout noise of 130 μVrms for the HCG signal and 1.19 V for the LCG input window.
  • The single-channel read-out chain reduced the area by half compared to traditional two-channel designs.
  • Demonstrated performance equivalent to 103 dB dynamic range.

Conclusions:

  • The proposed one-channel read-out circuit effectively reduces the area of LOFIC-CMOS image sensors.
  • This approach maintains high dynamic range performance while simplifying the sensor architecture.