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Gate-Level Circuit Partitioning Algorithm Based on Clustering and an Improved Genetic Algorithm.

Rui Cheng1, Lin-Zi Yin1, Zhao-Hui Jiang2

  • 1School of Physics and Electronics, Central South University, Changsha 410083, China.

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Summary
This summary is machine-generated.

This study introduces a novel gate-level circuit partitioning algorithm using clustering and genetic algorithms to enhance electronic design automation (EDA) simulation efficiency. The new method significantly reduces inter-partition connections compared to existing approaches.

Keywords:
betweenness centralitycircuit partitioningclustering algorithmgenetic algorithm

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Area of Science:

  • Computer Engineering
  • Algorithm Design
  • VLSI Design

Background:

  • Gate-level circuit partitioning is crucial for efficient Electronic Design Automation (EDA) software simulation.
  • Existing partitioning algorithms face challenges in optimizing simulation performance.

Purpose of the Study:

  • To propose an improved gate-level circuit partitioning algorithm for enhanced simulation efficiency.
  • To address the limitations of current partitioning methods in EDA.

Main Methods:

  • A novel algorithm combining betweenness centrality-based clustering for coarse partitioning.
  • A constraint-based genetic algorithm with specialized strategies for fine partitioning.
  • Utilized ISCAS '89 and ISCAS '85 benchmark circuits for evaluation.

Main Results:

  • The proposed algorithm achieved a significant reduction in the number of connections between subsets.
  • Demonstrated superior performance against Metis (5% better), KL (80% better), and traditional genetic algorithms (61% better).

Conclusions:

  • The developed algorithm effectively partitions gate-level circuits, improving simulation efficiency.
  • The hybrid clustering and genetic algorithm approach offers a robust solution for complex circuit partitioning tasks.