Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Concept Videos

Bipolar Junction Transistor01:22

Bipolar Junction Transistor

831
Bipolar Junction Transistors (BJTs) are essential elements in electronic circuits, playing a crucial role in the functionality of amplifiers, memories, and microprocessors. These transistors can be designed as NPN or PNP based on their doping patterns. They consist of three layers: the emitter, base, and collector. The configuration of these layers and their respective doping levels—with N-type or P-type impurities—define the transistor's type and its operational...
831
Biasing of P-N Junction01:16

Biasing of P-N Junction

630
The operation of a p-n junction diode involves various biasing conditions, including forward bias, reverse bias, and equilibrium.
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...
630
MOS Capacitor01:25

MOS Capacitor

868
A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
868
Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

289
Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
289
Biasing of FET01:22

Biasing of FET

330
Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the...
330
MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

402
Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
402

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

Reconfigurable Photoelectric Coaxial Fiber-Based Memristors for Neuromorphic Computing.

ACS nano·2026
Same author

Decoding motor imagery related to major mimetic muscles from electroencephalography.

Journal of neuroengineering and rehabilitation·2026
Same author

Exploring the Relationship Between Academic Stress and Academic Engagement in Chemistry Laboratory Learning: The Mediating Role of Learning Burnout and the Differentiated Roles of Stress Sources.

Behavioral sciences (Basel, Switzerland)·2026
Same author

Chrysophanol is associated with reduced inflammation and oxidative stress in sepsis-associated acute kidney injury.

Naunyn-Schmiedeberg's archives of pharmacology·2026
Same author

Influence of Device Structure and Manufacturing Thermal Budget on Channel Release Module in GAA NSFET and Process Optimization.

Nanomaterials (Basel, Switzerland)·2026
Same author

Surface energy-driven perpendicular gradient structure in flexible composite dielectrics for high-temperature capacitive energy storage.

Nature communications·2026
Same journal

Higher-Order Clustering of Receptors Real-Time Projected by Plasmon-ruler on the Single Live Cell.

Nano letters·2026
Same journal

Achieving Fermi-Level Depinning and Ideal Metal Contact in <i>β</i>-Ga<sub>2</sub>O<sub>3</sub> Devices via MXene Integration.

Nano letters·2026
Same journal

AI-Assisted Electron Microscopy in Structure-Performance Analysis of Advanced Catalysts: From Atomic Resolution to Statistical Significance.

Nano letters·2026
Same journal

Electrically Switchable Ultraslow Dispersionless Polaritons via Twist Engineering in van der Waals Heterostructures.

Nano letters·2026
Same journal

Correction to "Ultrasonication-Triggered Ubiquitous Assembly of Magnetic Janus Amphiphilic Nanoparticles in Cancer Theranostic Applications".

Nano letters·2026
Same journal

Tunable Proximity Valley Splitting Via Interfacial Exchange Pinning in WSe<sub>2</sub>-CrBr<sub>3</sub>-CrPS<sub>4</sub> Heterostructures.

Nano letters·2026
See all related articles

Related Experiment Video

Updated: Jul 29, 2025

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

7.9K

Reconfigurable Logic-in-Memory Computing Based on a Polarity-Controllable Two-Dimensional Transistor.

Zhe Sheng1, Jianguo Dong1, Wennan Hu1

  • 1School of Microelectronics, Fudan University, Shanghai 200433, China.

Nano Letters
|May 26, 2023
PubMed
Summary
This summary is machine-generated.

This study introduces a novel WSe2/h-BN/graphene transistor for efficient logic-in-memory applications. This device offers reconfigurable logic functions, significantly reducing transistor count and power consumption.

Keywords:
compacted transistorlogic-in-memoryreconfigurable logictwo-dimensional materials

More Related Videos

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
09:49

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

4.1K
A Method for Growing Bio-memristors from Slime Mold
07:46

A Method for Growing Bio-memristors from Slime Mold

Published on: November 2, 2017

9.0K

Related Experiment Videos

Last Updated: Jul 29, 2025

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

7.9K
In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
09:49

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

4.1K
A Method for Growing Bio-memristors from Slime Mold
07:46

A Method for Growing Bio-memristors from Slime Mold

Published on: November 2, 2017

9.0K

Area of Science:

  • Materials Science
  • Electrical Engineering
  • Computer Architecture

Background:

  • Logic-in-memory (LiM) architectures are crucial for high-performance, energy-efficient data processing.
  • Extending Moore's Law requires advanced transistor designs, such as 2D compacted transistors with integrated logic.
  • Conventional logic circuits demand numerous transistors, leading to high power consumption and area inefficiency.

Purpose of the Study:

  • To demonstrate a novel WSe2/h-BN/graphene based middle-floating-gate field-effect transistor (MFGFET) for LiM applications.
  • To achieve reconfigurable logic functions within a single device.
  • To significantly reduce transistor count and energy consumption compared to traditional designs.

Main Methods:

  • Fabrication of a WSe2/h-BN/graphene MFGFET.
  • Characterization of the transistor's electrical properties, including controllable polarity.
  • Demonstration of reconfigurable AND/XNOR logic functions by tuning gate and drain voltages.

Main Results:

  • The developed MFGFET exhibits tunable current levels and controllable polarity.
  • The device successfully performs reconfigurable AND/XNOR logic functions.
  • Significant reduction in transistor count: 75% for AND/NAND (from 4 to 1) and 87.5% for XNOR/XOR (from 8 to 1).

Conclusions:

  • The WSe2/h-BN/graphene MFGFET is a promising candidate for advanced logic-in-memory architectures.
  • This design offers substantial improvements in transistor efficiency and energy savings.
  • The reconfigurable nature of the device opens new possibilities for compact and efficient computing systems.