A Low-Phase-Noise 8 GHz Linear-Band Sub-Millimeter-Wave Phase-Locked Loop in 22 nm FD-SOI CMOS

Area of Science:

• Electrical Engineering
• Microwave Engineering
• Integrated Circuits

Background:

• Phased-locked loops (PLLs) are essential for high-data rate communication and imaging.
• Sub-millimeter-wave (sub-mm-wave) PLLs face challenges with noise and bandwidth due to parasitic capacitances.
• Existing sub-mm-wave PLLs often compromise on performance.

Purpose of the Study:

• To implement a low-phase noise and wideband integer-N, type-II PLL.
• To address the performance limitations of current sub-mm-wave PLLs.
• To achieve superior phase noise and bandwidth in the sub-mm-wave frequency range.

Main Methods:

• Design and fabrication of a type-II integer-N PLL using 22 nm FD-SOI CMOS technology.
• Integration of a wideband linear differential tuning I/Q voltage-controlled oscillator (VCO).
• Characterization of phase noise, frequency tuning range, output power, and power consumption.

Main Results:

• Achieved a wideband linear tuning range of 8 GHz within the 157.5-167.5 GHz frequency spectrum.
• Demonstrated a phase noise of -113 dBc/Hz @ 100 KHz from the VCO.
• The fabricated PLL exhibited phase noise below -103 dBc/Hz @ 1 KHz and -128 dBc/Hz @ 100 KHz, setting a new benchmark for sub-mm-wave PLLs.
• Measured RF output power of 2 dBm and DC power consumption of 120.75 mW.
• The compact chip size is 1.25 × 0.9 mm².

Conclusions:

• The implemented PLL offers the lowest phase noise for sub-mm-wave frequencies to date.
• The design successfully overcomes traditional limitations in sub-mm-wave PLL performance.
• This advancement is crucial for next-generation high-data rate communication and imaging systems.