Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers

Area of Science:

• Electrical Engineering
• Computer Engineering
• Nanotechnology

Background:

• Ternary Full Adders (TFA) are crucial components in ternary logic systems.
• Existing TFA designs using Carbon Nanotube Field-Effect Transistors (CNFETs) often have high transistor counts and energy consumption.
• Optimization is needed for efficient ternary arithmetic circuits.

Purpose of the Study:

• To propose novel, optimized Ternary Full Adder (TFA) designs using CNFETs.
• To reduce transistor count and energy consumption in ternary adders.
• To develop efficient 4-trit Ripple Carry Adders (RCA) based on the new TFA designs.

Main Methods:

• Developed two new TFA designs (TFA1 with 59 CNFETs, TFA2 with 55 CNFETs) utilizing unary operator gates and dual voltage supplies (Vdd, Vdd/2).
• Integrated the proposed TFAs into two 4-trit Ripple Carry Adders (RCA).
• Simulated the circuits using HSPICE with 32 nm CNFET technology under varying voltages, temperatures, and output loads.

Main Results:

• The proposed TFA designs achieved a significant reduction in energy consumption (Power Delay Product - PDP) by over 41%.
• The Energy Delay Product (EDP) was reduced by over 64%, indicating substantial improvements in energy efficiency and speed.
• The new designs outperform existing state-of-the-art ternary adder circuits in terms of energy efficiency.

Conclusions:

• The novel TFA designs offer a more efficient approach to ternary arithmetic circuit implementation.
• The proposed designs demonstrate significant reductions in power consumption and energy-delay product.
• These optimized CNFET-based ternary adders hold promise for low-power ternary computing applications.