Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data...

Area of Science:

• Neuromorphic Engineering
• Integrated Circuit Design
• Artificial Intelligence Hardware

Background:

• On-chip memory in neuromorphic chips consumes significant resources, limiting neuron density.
• Off-chip memory introduces power consumption and data access bottlenecks.

Purpose of the Study:

• To propose an on- and off-chip co-design approach for neuromorphic chips.
• To develop a figure of merit (FOM) for optimizing chip area, power, and data access bandwidth.
• To enhance neuron density and reduce power consumption in neuromorphic systems.

Main Methods:

• Developed a figure of merit (FOM) to evaluate design trade-offs.
• Employed deep multiplexing and weight-sharing technologies.
• Implemented a hybrid memory design for optimized on- and off-chip memory distribution.

Main Results:

• Achieved a 1.085× improvement over the baseline design based on FOM.
• Reduced on-chip storage pressure by 92.88% and total power by 27.86%.
• Fabricated a 10-core neuromorphic chip with 4.92 K/mm² core neuron density, a 3.39–30.56× improvement.

Conclusions:

• The co-design approach effectively balances chip area, power consumption, and data access bandwidth.
• The developed neuromorphic chip demonstrates high density and efficiency for SNN applications.
• This work offers a viable strategy for creating high-density, large-scale neuromorphic chips.