Transferable learning on analog hardware.

Area of Science:

• Photonics
• Artificial Intelligence
• Hardware Engineering

Background:

• Analog neural networks (NNs) offer significant energy and time savings but are vulnerable to static fabrication errors.
• Current training methods for photonic NN accelerators do not yield networks resilient to hardware imperfections.
• Existing error correction methods are impractical for large-scale deployment due to retraining needs, component demands, or hardware overhead.

Purpose of the Study:

• To develop novel training techniques for analog neural networks that enhance robustness against static hardware errors.
• To enable the practical deployment of photonic NN accelerators in real-world, error-prone environments.
• To address the limitations of existing error correction strategies in analog NN hardware.

Main Methods:

• Introduced one-time error-aware training methodologies for programmable photonic interferometer circuits.
• Developed techniques for training NNs that are inherently robust to static fabrication variations.
• Demonstrated the transferability of trained networks to arbitrary photonic NN hardware with significant errors.

Main Results:

• Achieved robust neural networks (NNs) that match the performance of ideal hardware.
• Successfully transferred trained NNs to faulty photonic hardware with errors up to five times larger than current fabrication tolerances.
• Overcame the need for individual retraining, stringent component quality, or hardware overhead associated with error correction.

Conclusions:

• One-time error-aware training is a viable solution for creating robust analog neural networks on photonic platforms.
• This approach significantly advances the practical application of energy-efficient analog NN accelerators.
• The developed techniques pave the way for deploying highly reliable photonic NNs in edge computing and other demanding applications.