A Picosecond Delay Generator Optimized by Layout and Routing Based on FPGA.

Area of Science:

• Electrical Engineering
• Computer Engineering

Background:

• Accurate timing control is crucial in various electronic systems.
• Existing delay generators may lack the required precision or scalability.

Purpose of the Study:

• To design and implement a high-resolution, high-accuracy delay generator.
• To propose a delay compensation scheme for improved theoretical model accuracy.
• To achieve low resource utilization on an FPGA.

Main Methods:

• Implementation of a delay generator on a Xilinx Kintex-7 FPGA.
• Utilizing a design scheme based on a carry delay chain.
• Developing a theoretical model with a delay compensation scheme.

Main Results:

• Achieved a time resolution of 54 ps.
• Demonstrated a time accuracy of less than 50 ps.
• The design exhibits high scalability for future improvements.

Conclusions:

• A scalable, high-performance delay generator was successfully implemented on an FPGA.
• The proposed design offers a practical solution for precise timing control with low resource occupancy.
• The theoretical model and compensation scheme enhance the relevance to actual circuit performance.