New Systolic Array Algorithms and VLSI Architectures for 1-D MDST.

Area of Science:

• Digital Signal Processing
• Integrated Circuit Design
• Computer Architecture

Background:

• The 1-D Modified Discrete Sine Transform (MDST) is crucial in various signal processing applications.
• Efficient Very-Large-Scale Integration (VLSI) implementations are essential for high-performance hardware.
• Existing systolic array approaches for MDST may face challenges in hardware complexity and efficiency.

Purpose of the Study:

• To develop novel systolic array algorithms for efficient VLSI implementation of the 1-D MDST.
• To reduce hardware complexity and improve the efficiency of MDST computation in VLSI.
• To leverage modular and regular computational structures for optimized hardware design.

Main Methods:

• Decomposition of the 1-D MDST into pseudo-circular correlation and pseudo-cycle convolution.
• Design of two distinct systolic array algorithms based on these structures.
• Exploitation of the common computational structure for hardware sharing.
• Optimization of multipliers in the second algorithm to further reduce complexity.

Main Results:

• The proposed algorithms enable efficient VLSI implementation of the 1-D MDST.
• Hardware complexity is significantly reduced by utilizing a shared linear systolic array.
• The second algorithm offers further complexity reduction through constant multipliers.
• Resulting architectures exhibit high-speed concurrency, efficient VLSI utilization, and low I/O cost.

Conclusions:

• The presented systolic array algorithms provide an efficient and cost-effective solution for VLSI-based 1-D MDST.
• The modular decomposition and architectural optimizations lead to reduced hardware complexity and improved performance.
• The architectures are suitable for high-speed applications and offer potential for secure implementations via obfuscation techniques.