NERONE: The Fast Way to Efficiently Execute Your Deep Learning Algorithm at the Edge.

Area of Science:

• Computer Vision
• Machine Learning
• Hardware Acceleration

Background:

• Deep learning (DL) models are crucial for clinical applications like radiation dose quantification and surgical planning.
• Graphics Processing Units (GPUs) are commonly used for DL inference but are power-intensive, limiting their use in constrained environments.
• Field Programmable Gate Arrays (FPGAs) offer superior performance-per-watt but are challenging for non-experts to utilize.

Purpose of the Study:

• To introduce NERONE, a tool that simplifies FPGA acceleration for DL models.
• To enable end-users to leverage FPGA energy efficiency without modifying existing DL development flows.
• To demonstrate NERONE's versatility across different network architectures and FPGA boards.

Main Methods:

• Developed four DL models (three for segmentation, one for classification) for diverse datasets.
• Deployed these models on embedded FPGA boards using the NERONE framework.
• Evaluated energy efficiency improvements compared to mobile and datacenter GPUs.

Main Results:

• NERONE facilitates the use of FPGAs for DL inference, making them accessible to a broader audience.
• Achieved an average energy efficiency improvement of 3.4x against mobile GPUs.
• Demonstrated an average energy efficiency improvement of 1.9x against datacenter GPUs.

Conclusions:

• NERONE effectively bridges the gap between DL development and FPGA hardware acceleration.
• The tool enhances energy efficiency for clinical DL applications, particularly in power-constrained settings.
• NERONE supports various network architectures, showcasing its adaptability and broad applicability.