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Updated: Jul 23, 2025

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Mobility Enhancement of Strained MoS2 Transistor on Flat Substrate
Yang Chen1, Donglin Lu1, Lingan Kong1
1Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics, Hunan University, Changsha 410082, China.
Strain engineering boosts two-dimensional (2D) semiconductor mobility. This study demonstrates a new method for applying pure lattice strain to Molybdenum Disulfide (MoS2) transistors, significantly enhancing electron mobility without substrate interference.
Area of Science:
- Materials Science
- Condensed Matter Physics
- Nanotechnology
Background:
- Strain engineering is a key strategy for enhancing carrier mobility in two-dimensional (2D) semiconductors.
- Current methods often involve flexible or nanostructured substrates, introducing confounding factors like dielectric variations and interface scattering.
- The precise impact of pure lattice strain on 2D semiconductor performance remains an open question.
Purpose of the Study:
- To develop a novel strain engineering technique for fabricating highly strained 2D semiconductor transistors on flat substrates.
- To investigate the effect of pure lattice strain on the carrier mobility of Molybdenum Disulfide (MoS2) transistors.
- To provide a reliable method for achieving high-performance 2D transistors through controlled strain application.
Main Methods:
- A mechanical lamination technique was employed to transfer prefabricated MoS2 transistors onto a custom-designed trench structure on a flat substrate.
- This method allows for uniform strain generation across the 2D channel while maintaining a flat substrate and dielectric interface.
- The strain was applied using controlled tension and compression.
Main Results:
- Electron mobility in MoS2 transistors was demonstrably enhanced by tensile strain and reduced by compressive strain, aligning with theoretical predictions.
- A maximum mobility enhancement of 152% was observed for monolayer MoS2 and 64% for bilayer MoS2 transistors.
- The strain engineering method ensured no roughness-induced scattering or dielectric environment changes.
Conclusions:
- The developed technique enables uniform strain application to layered semiconductors on flat, solid substrates.
- This method effectively boosts the carrier mobilities of 2D transistors, offering a pathway to high-performance devices.
- The findings confirm the significant role of pure lattice strain in modulating the electronic properties of 2D materials.
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