Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and...

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Science

Background:

• Analog in-memory computing synaptic devices are crucial for efficient deep learning.
• Resistive memory devices face challenges in on-chip training due to resistance control and device variations.
• Existing Si-CMOS and capacitor-based synapses suffer from insufficient retention time and accuracy degradation.

Purpose of the Study:

• To propose a novel 6T1C synaptic device for improved on-chip training in deep learning.
• To address limitations of existing synaptic devices, including resistance control, device variation, and retention time.
• To demonstrate the effectiveness of device-algorithm co-optimization for realistic training scenarios.

Main Methods:

• Development of a novel 6T1C synaptic device utilizing n-type Indium Gallium Zinc Oxide Thin Film Transistors (IGZO TFTs) and a capacitor.
• Implementation of linear and symmetric weight updates.
• Design of an efficient training algorithm to compensate for device non-idealities like drifting references and retention loss.

Main Results:

• The proposed IGZO TFT-based 6T1C device exhibits low leakage current, ensuring sufficient retention time.
• Achieved linear and symmetric weight updates, crucial for accurate learning.
• Demonstrated parallel on-chip training operations with improved accuracy.
• Validated the importance of device-algorithm co-optimization for overcoming remaining non-idealities.

Conclusions:

• The novel 6T1C IGZO TFT synaptic device offers a promising solution for efficient and accurate on-chip deep learning training.
• Device-algorithm co-optimization is essential for realizing the full potential of in-memory computing hardware.
• This approach overcomes key limitations of previous synaptic device technologies, paving the way for more robust AI hardware.